Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks

Abstract — The effects of parameter variations and crosstalk noise on the clock signal propagating along an H-tree clock distribution network are investigated in this paper. In particular, the effects of variations in power supply voltage (   ¢¡£

Buffer Sizing for Delay Uncertainty Induced by Process Variations

Controlling the delay of a signal in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high performance synchronous circuits. The effects of device parameter variations on the signal propagation delay of a CMOS buffer are described in this paper. It is shown that delay uncertainty is introduced due to variations in the current flow through a buffer. In addition, the variations in the parasitic resistance and capacitance of an interconnect line also affect the buffer delay. A design methodology that reduces the delay uncertainty of signals propagating along buffer-driven interconnect lines is presented. The proposed methodology increases the current flow sourced by a buffer to reduce the sensitivity of the delay on device and interconnect parameter variations. 1

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A polynomial time algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay to the most critical data paths. Strategies for enhancing the physical layout of the clock tree to decrease delay uncertainty are also presented. Application of the methodology on benchmark circuits demonstrates clock tree topologies with decreased delay uncertainties of up to 90%. Techniques to enhance a clock tree layout have been applied on a set of benchmark circuits, yielding a reduction in delay uncertainty of up to 48%. 1

Clock Tree Layout Design for Reduced Delay Uncertainty

Abstract — The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. Two different approaches for enhancing the layout of the clock tree in order to reduce the uncertainty of the clock signal are presented in this paper. The application of these techniques on a set of benchmark circuits demonstrates interesting tradeoffs among the aggregate clock buffer size, the total wire length of the clock tree, and the power dissipation. I

A Clock Tree Topology Extraction Algorithm for Improving the Tolerance of Clock Distribution Networks to Delay Uncertainty

The design of clock distribution networks in synchronous systems presents enormous challenges. Control of the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents one of the fundamental problems in the design of high speed synchronous circuits. An algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay in the most critical data paths. Details of the algorithm and preliminary results on benchmark circuits are presented. 1

Effects of Process and Enviromental Variations on Adder Architectures

Abstract — Scaling of the on-chip feature size and power supply voltage have significantly reduced the noise margins of an integrated circuit and have aggravated the effects of process and enviromental variations. These effects can introduce delay variations on the signals within a circuit, possibly causing a violation of the timing constraints in a clocked register that can lead to system malfunctioning. The effects of parameter variations on the timing characteristics of adder structures are investigated in this paper. The sensitivity of the critical delay of sum and carry signals under variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different adder architectures. I

Reduced Delay Uncertainty in High Performance Clock Distribution Networks

The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A polynomial time algorithm that improves the tolerance of a clock distribution network to process and environmental variations is presented in this paper. The algorithm generates a clock tree topology that minimizes the uncertainty of the clock signal delay to the most critical data paths. Strategies for enhancing the physical layout of the clock tree to decrease delay uncertainty are also presented. Application of the methodology on benchmark circuits demonstrates clock tree topologies with decreased delay uncertainties of up to 90%. Techniques to enhance a clock tree layout have been applied on a set of benchmark circuits, yielding a reduction in delay uncertainty of up to 48%